In a digital communications system it is frequently necessary to accept data from a remote source and synchronize it to a local or output clock. One example of this is an incoming time division multiplex (TDM) data stream the various data channels of which must be routed to separate destinations through a TDM switching center. A conventional way of handling this situation is to use a double rank register. The received data is shifted in serially by the received or input clock, a parallel transfer is made to the output register, and the data is sent out under the control of the local or output clock. This method is useful for transferring short bursts of data.
Where two asynchronous systems must be buffered for longer intervals, random access memories are used. The technique is to write the input data into the random access memory using the received clock to operate a sequential address counter. At some later time, the memory is read out by addressing it through a counter operated by the local or output clock. While the data is being read out, the new received data must be stored in a different memory chip because a memory cannot be written into and read from simultaneously. This method therefore requires a multiplicity of memory chips, and the arrangement overflows when both input and output address counters attempt to access the same memory chip.
This problem has been partially overcome by the use of an elastic buffer, as the one described in U.S. Pat. No. 4,056,851 which includes a single random access memory from which information bits are read out at a rate determined by an output clock, and into which received information bits are written at a rate determined by an input clock, where the two clocks are not exactly synchronous. Timing and storage means are provided to accommodate the zero, one or two information bits, which may be received for storage in the memory, in the interval between the readout of two successive information bits from the memory. An alarm is given if the input and output clock rates are such that the memory is emptied, or is filled and about to overflow.
The elastic buffer described in the above cited patent, even if it provides an interesting alternative to the conventional first-in-first-out (FIFO) buffers, does not solve several supplementary problems. In particular, the provision for a buffering RAM is not enough to avoid the necessity for substantial external data and clock buffering, using registers. Further, the elasticity between the two asynchronous data flows is limited to one or two bits, which excludes the possibility of asynchronous transmission and buffering of several bytes of data. Moreover, the reception of data by the elastic buffer, and the retransmission of data remain two successive and alternating operations of a FLIP-FLOP type, which, in view of the limited capacity of the elastic buffer, affects the throughput of the buffer, and consequently, of the data transmission between the asynchronous emitter and receiver.